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By Edmund Callis Berkeley

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First, all the biasing circuits are kept on with the exception of therefore and are kept constant during both phases, so the turn-on time for the OTA core is minimized. Second, the control switch can be turned off before the to transition, making the OTA return to normal biasing conditions before it enters the amplifying phase. 17. Low Power ADC Design 37 In summary, the existence of an idle state in the pipeline interstage gain amplifier makes the dynamic biasing a practical way to save power consumptions.

4 Amplifier Requirements Finite gain and incomplete settling of amplifiers cause errors in pipeline ADCs. In this section, the requirements for amplifiers in high-speed high-resolution ADCs are analyzed. 1 DC-Gain Requirement: For a finite opamp gain A, the relationship between the output and input of an interstage gain-amplifier can be written as: Low Power ADC Design 29 where is the feedback factor, and is the input capacitance of the amplifier. If A · then the gain error of the interstage amplifier can be expressed as: 30 DATA CONVERTERS FOR WIRELESS STANDARDS For a N-bit ADC with a B-bit/stage architecture, the first stage gain error should be less than 1/2 LSB of the full range of the second stage to prevent any missing codes.

4 shows the block diagram of a two-step ADC. The MSB subADC obtains N/2 most-significant-bits (MSBs) from the input sampled signal, and the sub-DAC block converts the MSBs back to an analog signal, while the residue between the sampled signal and this analog signal is passed to the LSB sub-ADC where the least-significant-bits (LSBs) are obtained. Compared to the flash architecture, a two-step ADC requires less comparators has less input capacitance, with relaxed requirements on the comparator. The main drawback is that it requires precise inter-stage processing, which is not an easy task at high sampling frequencies.

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Computers: their operation and applications by Edmund Callis Berkeley


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